Definition at line 354 of file v1724_module.c.
References CAEN_DGTZ_BROAD_CH_CTRL_ADD, CAEN_DGTZ_ClearData(), CAEN_DGTZ_ReadRegister(), CAEN_DGTZ_Reset(), CAEN_DGTZ_SetAcquisitionMode(), CAEN_DGTZ_SetChannelDCOffset(), CAEN_DGTZ_SetChannelEnableMask(), CAEN_DGTZ_SetChannelPulsePolarity(), CAEN_DGTZ_SetChannelSelfTrigger(), CAEN_DGTZ_SetChannelTriggerThreshold(), CAEN_DGTZ_SetChannelZSParams(), CAEN_DGTZ_SetPostTriggerSize(), CAEN_DGTZ_SetRecordLength(), CAEN_DGTZ_SetTriggerPolarity(), CAEN_DGTZ_SetZeroSuppressionMode(), CAEN_DGTZ_Success, CAEN_DGTZ_SWStartAcquisition(), CAEN_DGTZ_TRGMODE_ACQ_AND_EXTOUT, CAEN_DGTZ_TRGMODE_ACQ_ONLY, CAEN_DGTZ_TRGMODE_DISABLED, CAEN_DGTZ_TRGMODE_EXTOUT_ONLY, CAEN_DGTZ_TriggerOnFallingEdge, CAEN_DGTZ_TriggerOnRisingEdge, CAEN_DGTZ_WriteRegister(), CAEN_DGTZ_ZS_FINE, CAEN_DGTZ_ZS_ZLE, data_size, enabled, handle, NBOARDS, printf(), SUCCESS, and s_v1724_odb::trigger_edge.
358 for (
int iboard=0; iboard<
NBOARDS; iboard++)
369 cm_msg(MERROR,
"v1724_init",
"Cannot reset the board. Error 0x%08x\n",ret);
376 uint32_t channel_mask = 0x0;
377 for (uint32_t ichan=0; ichan<8; ichan++)
380 channel_mask |= (1 << ichan);
382 printf(
"channel enable mask: 0x%08x\n",channel_mask);
386 cm_msg(MERROR,
"v1724_init",
"Cannot Enable channels. Error 0x%08x\n",ret);
397 cm_msg(MERROR,
"v1724_init",
"Cannot configure Acquisition Control. Error 0x%08x\n",ret);
410 cm_msg(MERROR,
"v1724_init",
"Cannot SetRecordLength. Error 0x%08x\n",ret);
419 uint32_t self_trigger_mask = 0x0;
420 for (uint32_t ichan=0; ichan<8; ichan++)
423 self_trigger_mask |= (1 << ichan);
425 printf(
"self-trigger DISABLED mask: 0x%08x\n",channel_mask);
429 cm_msg(MERROR,
"v1724_init",
"Cannot SetCahnngelSelfTrigger. Error 0x%08x\n",ret);
434 self_trigger_mask = 0x0;
435 for (uint32_t ichan=0; ichan<8; ichan++)
438 self_trigger_mask |= (1 << ichan);
440 printf(
"self-trigger ACQ_ONLY mask: 0x%08x\n",channel_mask);
444 cm_msg(MERROR,
"v1724_init",
"Cannot SetCahnngelSelfTrigger. Error 0x%08x\n",ret);
450 self_trigger_mask = 0x0;
451 for (uint32_t ichan=0; ichan<8; ichan++)
454 self_trigger_mask |= (1 << ichan);
456 printf(
"self-trigger EXTOUT_ONLY mask: 0x%08x\n",channel_mask);
460 cm_msg(MERROR,
"v1724_init",
"Cannot SetCahnngelSelfTrigger. Error 0x%08x\n",ret);
466 self_trigger_mask = 0x0;
467 for (uint32_t ichan=0; ichan<8; ichan++)
470 self_trigger_mask |= (1 << ichan);
472 printf(
"self-trigger ACQ_AND_EXTOUT mask: 0x%08x\n",channel_mask);
476 cm_msg(MERROR,
"v1724_init",
"Cannot SetCahnngelSelfTrigger. Error 0x%08x\n",ret);
485 if ( trigger_edge == 0 )
491 cm_msg(MERROR,
"v1724_init",
"Cannot SetTriggerPolarity. Error 0x%08x\n",ret);
498 for (uint32_t ichan=0; ichan<8; ichan++)
503 cm_msg(MERROR,
"v1724_init",
"Cannot SetChannelTriggerThreshold. Error 0x%08x\n",ret);
512 for (uint32_t ichan=0; ichan<8; ichan++)
514 uint32_t addr = V1724_BASE[iboard]+0x1084 + 0x100*ichan;
518 cm_msg(MERROR,
"v1724_init",
"Cannot Set the number of samples over threshold for trigger. Error 0x%08x\n",ret);
531 cm_msg(MERROR,
"v1724_init",
"Cannot SetPostTriggerSize. Error 0x%08x\n",ret);
539 for (uint32_t ichan=0; ichan<8; ichan++)
544 cm_msg(MERROR,
"v1724_init",
"Cannot SetChannelDCOffset. Error 0x%08x\n",ret);
553 for (uint32_t ichan=0; ichan<8; ichan++)
560 cm_msg(MERROR,
"v1724_init",
"Cannot SetChannelPulsePolarity. Error 0x%08x\n",ret);
570 for (uint32_t ichan=0; ichan<8; ichan++)
575 cm_msg(MERROR,
"v1724_init",
"Cannot SetChannelZSParams. Error 0x%08x\n",ret);
587 cm_msg(MERROR,
"v1724_init",
"Cannot SetZeroSuppressionMode. Error 0x%08x\n",ret);
598 cm_msg(MERROR,
"v1724_init",
"Cannot clear CAEN data buffers. Error 0x%08x\n",ret);
608 cm_msg(MERROR,
"v1724_init",
"Cannot CAEN_DGTZ_SWStartAcquisition. Error 0x%08x\n",ret);
622 cm_msg(MERROR,
"v1724_init",
"Cannot read from register 0x8000. Error 0x%08x\n",ret);
628 printf(
"channel configuration register 0x8000: %0x08x\n",data);
632 cm_msg(MERROR,
"v1724_init",
"Cannot write to register 0x8000. Error 0x%08x\n",ret);