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24 #ifndef __CAENDIGITIZERTYPE_H
25 #define __CAENDIGITIZERTYPE_H
29 #define CAENDGTZ_API __stdcall
32 #include <sys/types.h>
55 #define uint16_t UINT16
58 #define uint32_t UINT32
61 #define uint64_t UINT64
66 #define MAX_UINT16_CHANNEL_SIZE 64
67 #define MAX_UINT8_CHANNEL_SIZE 8
68 #define MAX_V1724DPP_CHANNEL_SIZE 8
69 #define MAX_V1720DPP_CHANNEL_SIZE 8
70 #define MAX_ZLE_CHANNEL_SIZE 8
71 #define MAX_X742_CHANNEL_SIZE 9
72 #define MAX_X742_GROUP_SIZE 4
73 #define MAX_X743_CHANNELS_X_GROUP 2
74 #define MAX_V1743_GROUP_SIZE 8
75 #define MAX_DT5743_GROUP_SIZE 4
76 #define MAX_V1723_CHANNEL_SIZE 16
82 #define CAEN_DGTZ_MULTI_EVENT_BUFFER 0x0000
84 #define CAEN_DGTZ_CHANNEL_ZS_THRESHOLD_BASE_ADDRESS 0x1024
85 #define CAEN_DGTZ_CHANNEL_ZS_NSAMPLE_BASE_ADDRESS 0x1028
86 #define CAEN_DGTZ_CHANNEL_THRESHOLD_BASE_ADDRESS 0x1080
87 #define CAEN_DGTZ_CHANNEL_OV_UND_TRSH_BASE_ADDRESS 0x1084
88 #define CAEN_DGTZ_CHANNEL_STATUS_BASE_ADDRESS 0x1088
89 #define CAEN_DGTZ_CHANNEL_AMC_FPGA_FW_BASE_ADDRESS 0x108C
90 #define CAEN_DGTZ_CHANNEL_BUFFER_OCC_BASE_ADDRESS 0x1094
91 #define CAEN_DGTZ_CHANNEL_DAC_BASE_ADDRESS 0x1098
92 #define CAEN_DGTZ_CHANNEL_GROUP_V1740_BASE_ADDRESS 0x10A8
93 #define CAEN_DGTZ_GROUP_FASTTRG_THR_V1742_BASE_ADDRESS 0x10D4
94 #define CAEN_DGTZ_GROUP_FASTTRG_DCOFFSET_V1742_BASE_ADDRESS 0x10DC
95 #define CAEN_DGTZ_DRS4_FREQUENCY_REG 0x10D8
96 #define CAEN_DGTZ_SAM_FREQUENCY_REG 0x1040
97 #define CAEN_DGTZ_SAM_PRE_TRSH_REG 0x104B
98 #define CAEN_DGTZ_SAM_BSL_TRSH_RED 0x1048
99 #define CAEN_DGTZ_SAM_TRIGGER_REG_ADD 0x103B
102 #define CAEN_DGTZ_BROAD_CH_CTRL_ADD 0x8000
103 #define CAEN_DGTZ_BROAD_CH_CONFIGBIT_SET_ADD 0x8004
104 #define CAEN_DGTZ_BROAD_CH_CLEAR_CTRL_ADD 0x8008
105 #define CAEN_DGTZ_BROAD_NUM_BLOCK_ADD 0x800C
106 #define CAEN_DGTZ_CUSTOM_SIZE_REG 0x8020
107 #define CAEN_DGTZ_DPP_NUM_EVENTS_PER_AGGREGATE 0x8034
108 #define CAEN_DGTZ_DRS4_FREQUENCY_REG_WRITE 0x80D8
109 #define CAEN_DGTZ_SAM_FREQUENCY_REG_WRITE 0x8040
110 #define CAEN_DGTZ_SAM_REG_ADD 0x8084
111 #define CAEN_DGTZ_SAM_REG_VALUE 0x8028
112 #define CAEN_DGTZ_SAM_DAC_SPI_DATA_ADD 0x8054
113 #define CAEN_DGTZ_SAM_CTRL_ADD 0x8070
114 #define CAEN_DGTZ_SAM_START_ACQ_ADD 0x8018
115 #define CAEN_DGTZ_SAM_RESET_ACQ_ADD 0x805B
116 #define CAEN_DGTZ_SAM_NB_OF_COLS_2_READ_ADD 0x8044
117 #define CAEN_DGTZ_SAM_POST_TRIGGER_ADD 0x8030
118 #define CAEN_DGTZ_ACQ_CONTROL_ADD 0x8100
119 #define CAEN_DGTZ_ACQ_STATUS_ADD 0x8104
120 #define CAEN_DGTZ_SW_TRIGGER_ADD 0x8108
121 #define CAEN_DGTZ_TRIGGER_SRC_ENABLE_ADD 0x810C
122 #define CAEN_DGTZ_FP_TRIGGER_OUT_ENABLE_ADD 0x8110
123 #define CAEN_DGTZ_POST_TRIG_ADD 0x8114
124 #define CAEN_DGTZ_FRONT_PANEL_IO_ADD 0x8118
125 #define CAEN_DGTZ_FRONT_PANEL_IO_CTRL_ADD 0x811C
126 #define CAEN_DGTZ_CH_ENABLE_ADD 0x8120
127 #define CAEN_DGTZ_FW_REV_ADD 0x8124
128 #define CAEN_DGTZ_DOWNSAMPLE_FACT_ADD 0x8128
129 #define CAEN_DGTZ_EVENT_STORED_ADD 0x812C
130 #define CAEN_DGTZ_MON_SET_ADD 0x8138
131 #define CAEN_DGTZ_BOARD_INFO_ADD 0x8140
132 #define CAEN_DTGZ_EVENT_SIZE_ADD 0x814C
133 #define CAEN_DGTZ_MON_MODE_ADD 0x8144
134 #define CAEN_DGTZ_ANALOG_MON_ADD 0x8150
136 #define CAEN_DGTZ_VME_CONTROL_ADD 0xEF00
137 #define CAEN_DGTZ_VME_STATUS_ADD 0xEF04
138 #define CAEN_DGTZ_BOARD_ID_ADD 0xEF08
139 #define CAEN_DGTZ_MCST_CBLT_ADD_CTRL_ADD 0xEF0C
140 #define CAEN_DGTZ_RELOCATION_ADDRESS_ADD 0xEF10
141 #define CAEN_DGTZ_INT_STATUS_ID_ADD 0xEF14
142 #define CAEN_DGTZ_INT_EVENT_NUM_ADD 0xEF18
143 #define CAEN_DGTZ_BLT_EVENT_NUM_ADD 0xEF1C
144 #define CAEN_DGTZ_SCRATCH_ADD 0xEF20
145 #define CAEN_DGTZ_SW_RESET_ADD 0xEF24
146 #define CAEN_DGTZ_SW_CLEAR_ADD 0xEF28
147 #define CAEN_DGTZ_FLASH_EN_ADD 0xEF2C
148 #define CAEN_DGTZ_FLASH_DATA_ADD 0xEF30
149 #define CAEN_DGTZ_RELOAD_CONFIG_ADD 0xEF34
151 #define CAEN_DGTZ_ROM_CHKSUM_ADD 0xF000
152 #define CAEN_DGTZ_ROM_CHKSUM_LEN_2_ADD 0xF004
153 #define CAEN_DGTZ_ROM_CHKSUM_LEN_1_ADD 0xF008
154 #define CAEN_DGTZ_ROM_CHKSUM_LEN_0_ADD 0xF00C
155 #define CAEN_DGTZ_ROM_CONST_2_ADD 0xF010
156 #define CAEN_DGTZ_ROM_CONST_1_ADD 0xF014
157 #define CAEN_DGTZ_ROM_CONST_0_ADD 0xF018
158 #define CAEN_DGTZ_ROM_C_CODE_ADD 0xF01C
159 #define CAEN_DGTZ_ROM_R_CODE_ADD 0xF020
160 #define CAEN_DGTZ_ROM_OUI_2_ADD 0xF024
161 #define CAEN_DGTZ_ROM_OUI_1_ADD 0xF028
162 #define CAEN_DGTZ_ROM_OUI_0_ADD 0xF02C
163 #define CAEN_DGTZ_ROM_VERSION_ADD 0xF030
164 #define CAEN_DGTZ_ROM_BOARD_ID_2_ADD 0xF034
165 #define CAEN_DGTZ_ROM_BOARD_ID_1_ADD 0xF038
166 #define CAEN_DGTZ_ROM_BOARD_ID_0_ADD 0xF03C
167 #define CAEN_DGTZ_ROM_REVISION_3_ADD 0xF040
168 #define CAEN_DGTZ_ROM_REVISION_2_ADD 0xF044
169 #define CAEN_DGTZ_ROM_REVISION_1_ADD 0xF048
170 #define CAEN_DGTZ_ROM_REVISION_0_ADD 0xF04C
171 #define CAEN_DGTZ_ROM_SERIAL_1_ADD 0xF080
172 #define CAEN_DGTZ_ROM_SERIAL_0_ADD 0xF084
173 #define CAEN_DGTZ_ROM_VCXO_TYPE_ADD 0xF088
177 #define CAEN_DGTZ_InputDCOffsetReg_Ch(x) (0x1098 | ((x)<<8))
178 #define CAEN_DGTZ_ChannelFWRevisionReg_Ch(x) (0x108C | ((x)<<8))
179 #define CAEN_DGTZ_DPP1Reg_Ch(x) (0x1024 | ((x)<<8))
180 #define CAEN_DGTZ_DPP2Reg_Ch(x) (0x1028 | ((x)<<8))
181 #define CAEN_DGTZ_DPP3Reg_Ch(x) (0x102C | ((x)<<8))
224 #define CAEN_DGTZ_MAX_CHANNEL 8
746 char ROC_FirmwareRel[20];
747 char AMC_FirmwareRel[40];
907 #define CAEN_DGTZ_DPP_CI_Waveforms_t CAEN_DGTZ_DPP_PSD_Waveforms_t
909 #define CAEN_DGTZ_AutoAggregation 0
920 #define CAEN_DGTZ_DPP_CI_PUR_DetectOnly CAEN_DGTZ_DPP_PSD_PUR_DetectOnly
921 #define CAEN_DGTZ_DPP_CI_PUR_Enabled CAEN_DGTZ_DPP_PSD_PUR_Enabled