AlcapDAQ  1
CAENDigitizerType.h
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1 /******************************************************************************
2 *
3 * CAEN SpA - Computing Division
4 * Via Vetraia, 11 - 55049 - Viareggio ITALY
5 * +390594388398 - www.caen.it
6 *
7 ***************************************************************************/
24 #ifndef __CAENDIGITIZERTYPE_H
25 #define __CAENDIGITIZERTYPE_H
26 
27 #ifdef WIN32
28  #include <windows.h>
29  #define CAENDGTZ_API __stdcall
30 #else
31  #include <sys/time.h>
32  #include <sys/types.h>
33  #include <unistd.h>
34  #include <stdint.h>
35  #define CAENDGTZ_API
36 #endif
37 
38 #ifdef WIN32
39  #ifndef int8_t
40  #define int8_t INT8
41  #endif
42  #ifndef int16_t
43  #define int16_t INT16
44  #endif
45  #ifndef int32_t
46  #define int32_t INT32
47  #endif
48  #ifndef int64_t
49  #define int64_t INT64
50  #endif
51  #ifndef uint8_t
52  #define uint8_t UINT8
53  #endif
54  #ifndef uint16_t
55  #define uint16_t UINT16
56  #endif
57  #ifndef uint32_t
58  #define uint32_t UINT32
59  #endif
60  #ifndef uint64_t
61  #define uint64_t UINT64
62  #endif
63 #endif
64 
65 
66 #define MAX_UINT16_CHANNEL_SIZE 64
67 #define MAX_UINT8_CHANNEL_SIZE 8
68 #define MAX_V1724DPP_CHANNEL_SIZE 8
69 #define MAX_V1720DPP_CHANNEL_SIZE 8
70 #define MAX_ZLE_CHANNEL_SIZE 8
71 #define MAX_X742_CHANNEL_SIZE 9
72 #define MAX_X742_GROUP_SIZE 4
73 #define MAX_X743_CHANNELS_X_GROUP 2
74 #define MAX_V1743_GROUP_SIZE 8
75 #define MAX_DT5743_GROUP_SIZE 4
76 #define MAX_V1723_CHANNEL_SIZE 16
77 
78 /******************************************************************************
79 * Digitizer Registers Address Map
80 ******************************************************************************/
81 
82 #define CAEN_DGTZ_MULTI_EVENT_BUFFER 0x0000
83 
84 #define CAEN_DGTZ_CHANNEL_ZS_THRESHOLD_BASE_ADDRESS 0x1024
85 #define CAEN_DGTZ_CHANNEL_ZS_NSAMPLE_BASE_ADDRESS 0x1028
86 #define CAEN_DGTZ_CHANNEL_THRESHOLD_BASE_ADDRESS 0x1080
87 #define CAEN_DGTZ_CHANNEL_OV_UND_TRSH_BASE_ADDRESS 0x1084
88 #define CAEN_DGTZ_CHANNEL_STATUS_BASE_ADDRESS 0x1088
89 #define CAEN_DGTZ_CHANNEL_AMC_FPGA_FW_BASE_ADDRESS 0x108C
90 #define CAEN_DGTZ_CHANNEL_BUFFER_OCC_BASE_ADDRESS 0x1094
91 #define CAEN_DGTZ_CHANNEL_DAC_BASE_ADDRESS 0x1098
92 #define CAEN_DGTZ_CHANNEL_GROUP_V1740_BASE_ADDRESS 0x10A8
93 #define CAEN_DGTZ_GROUP_FASTTRG_THR_V1742_BASE_ADDRESS 0x10D4
94 #define CAEN_DGTZ_GROUP_FASTTRG_DCOFFSET_V1742_BASE_ADDRESS 0x10DC
95 #define CAEN_DGTZ_DRS4_FREQUENCY_REG 0x10D8
96 #define CAEN_DGTZ_SAM_FREQUENCY_REG 0x1040
97 #define CAEN_DGTZ_SAM_PRE_TRSH_REG 0x104B
98 #define CAEN_DGTZ_SAM_BSL_TRSH_RED 0x1048
99 #define CAEN_DGTZ_SAM_TRIGGER_REG_ADD 0x103B
100 
101 
102 #define CAEN_DGTZ_BROAD_CH_CTRL_ADD 0x8000
103 #define CAEN_DGTZ_BROAD_CH_CONFIGBIT_SET_ADD 0x8004
104 #define CAEN_DGTZ_BROAD_CH_CLEAR_CTRL_ADD 0x8008
105 #define CAEN_DGTZ_BROAD_NUM_BLOCK_ADD 0x800C
106 #define CAEN_DGTZ_CUSTOM_SIZE_REG 0x8020
107 #define CAEN_DGTZ_DPP_NUM_EVENTS_PER_AGGREGATE 0x8034
108 #define CAEN_DGTZ_DRS4_FREQUENCY_REG_WRITE 0x80D8
109 #define CAEN_DGTZ_SAM_FREQUENCY_REG_WRITE 0x8040
110 #define CAEN_DGTZ_SAM_REG_ADD 0x8084
111 #define CAEN_DGTZ_SAM_REG_VALUE 0x8028
112 #define CAEN_DGTZ_SAM_DAC_SPI_DATA_ADD 0x8054
113 #define CAEN_DGTZ_SAM_CTRL_ADD 0x8070
114 #define CAEN_DGTZ_SAM_START_ACQ_ADD 0x8018
115 #define CAEN_DGTZ_SAM_RESET_ACQ_ADD 0x805B
116 #define CAEN_DGTZ_SAM_NB_OF_COLS_2_READ_ADD 0x8044
117 #define CAEN_DGTZ_SAM_POST_TRIGGER_ADD 0x8030
118 #define CAEN_DGTZ_ACQ_CONTROL_ADD 0x8100
119 #define CAEN_DGTZ_ACQ_STATUS_ADD 0x8104
120 #define CAEN_DGTZ_SW_TRIGGER_ADD 0x8108
121 #define CAEN_DGTZ_TRIGGER_SRC_ENABLE_ADD 0x810C
122 #define CAEN_DGTZ_FP_TRIGGER_OUT_ENABLE_ADD 0x8110
123 #define CAEN_DGTZ_POST_TRIG_ADD 0x8114
124 #define CAEN_DGTZ_FRONT_PANEL_IO_ADD 0x8118
125 #define CAEN_DGTZ_FRONT_PANEL_IO_CTRL_ADD 0x811C
126 #define CAEN_DGTZ_CH_ENABLE_ADD 0x8120
127 #define CAEN_DGTZ_FW_REV_ADD 0x8124
128 #define CAEN_DGTZ_DOWNSAMPLE_FACT_ADD 0x8128
129 #define CAEN_DGTZ_EVENT_STORED_ADD 0x812C
130 #define CAEN_DGTZ_MON_SET_ADD 0x8138
131 #define CAEN_DGTZ_BOARD_INFO_ADD 0x8140
132 #define CAEN_DTGZ_EVENT_SIZE_ADD 0x814C
133 #define CAEN_DGTZ_MON_MODE_ADD 0x8144
134 #define CAEN_DGTZ_ANALOG_MON_ADD 0x8150
135 
136 #define CAEN_DGTZ_VME_CONTROL_ADD 0xEF00
137 #define CAEN_DGTZ_VME_STATUS_ADD 0xEF04
138 #define CAEN_DGTZ_BOARD_ID_ADD 0xEF08
139 #define CAEN_DGTZ_MCST_CBLT_ADD_CTRL_ADD 0xEF0C
140 #define CAEN_DGTZ_RELOCATION_ADDRESS_ADD 0xEF10
141 #define CAEN_DGTZ_INT_STATUS_ID_ADD 0xEF14
142 #define CAEN_DGTZ_INT_EVENT_NUM_ADD 0xEF18
143 #define CAEN_DGTZ_BLT_EVENT_NUM_ADD 0xEF1C
144 #define CAEN_DGTZ_SCRATCH_ADD 0xEF20
145 #define CAEN_DGTZ_SW_RESET_ADD 0xEF24
146 #define CAEN_DGTZ_SW_CLEAR_ADD 0xEF28
147 #define CAEN_DGTZ_FLASH_EN_ADD 0xEF2C
148 #define CAEN_DGTZ_FLASH_DATA_ADD 0xEF30
149 #define CAEN_DGTZ_RELOAD_CONFIG_ADD 0xEF34
150 
151 #define CAEN_DGTZ_ROM_CHKSUM_ADD 0xF000
152 #define CAEN_DGTZ_ROM_CHKSUM_LEN_2_ADD 0xF004
153 #define CAEN_DGTZ_ROM_CHKSUM_LEN_1_ADD 0xF008
154 #define CAEN_DGTZ_ROM_CHKSUM_LEN_0_ADD 0xF00C
155 #define CAEN_DGTZ_ROM_CONST_2_ADD 0xF010
156 #define CAEN_DGTZ_ROM_CONST_1_ADD 0xF014
157 #define CAEN_DGTZ_ROM_CONST_0_ADD 0xF018
158 #define CAEN_DGTZ_ROM_C_CODE_ADD 0xF01C
159 #define CAEN_DGTZ_ROM_R_CODE_ADD 0xF020
160 #define CAEN_DGTZ_ROM_OUI_2_ADD 0xF024
161 #define CAEN_DGTZ_ROM_OUI_1_ADD 0xF028
162 #define CAEN_DGTZ_ROM_OUI_0_ADD 0xF02C
163 #define CAEN_DGTZ_ROM_VERSION_ADD 0xF030
164 #define CAEN_DGTZ_ROM_BOARD_ID_2_ADD 0xF034
165 #define CAEN_DGTZ_ROM_BOARD_ID_1_ADD 0xF038
166 #define CAEN_DGTZ_ROM_BOARD_ID_0_ADD 0xF03C
167 #define CAEN_DGTZ_ROM_REVISION_3_ADD 0xF040
168 #define CAEN_DGTZ_ROM_REVISION_2_ADD 0xF044
169 #define CAEN_DGTZ_ROM_REVISION_1_ADD 0xF048
170 #define CAEN_DGTZ_ROM_REVISION_0_ADD 0xF04C
171 #define CAEN_DGTZ_ROM_SERIAL_1_ADD 0xF080
172 #define CAEN_DGTZ_ROM_SERIAL_0_ADD 0xF084
173 #define CAEN_DGTZ_ROM_VCXO_TYPE_ADD 0xF088
174 
175 
176 // INDIVIDUAL CHANNEL ADDRESSING
177 #define CAEN_DGTZ_InputDCOffsetReg_Ch(x) (0x1098 | ((x)<<8))
178 #define CAEN_DGTZ_ChannelFWRevisionReg_Ch(x) (0x108C | ((x)<<8))
179 #define CAEN_DGTZ_DPP1Reg_Ch(x) (0x1024 | ((x)<<8))
180 #define CAEN_DGTZ_DPP2Reg_Ch(x) (0x1028 | ((x)<<8))
181 #define CAEN_DGTZ_DPP3Reg_Ch(x) (0x102C | ((x)<<8))
182 
183 
184 /*###########################################################################*/
185 /*
186 ** ErrorCode
187 */
188 /*###########################################################################*/
189 typedef enum CAEN_DGTZ_ErrorCode {
190 CAEN_DGTZ_Success = 0L, /* Operation completed successfully */
191 CAEN_DGTZ_CommError = -1L, /* Communication error */
192 CAEN_DGTZ_GenericError = -2L, /* Unspecified error */
193 CAEN_DGTZ_InvalidParam = -3L, /* Invalid parameter */
194 CAEN_DGTZ_InvalidLinkType = -4L, /* Invalid Link Type */
195 CAEN_DGTZ_InvalidHandle = -5L, /* Invalid device handle */
196 CAEN_DGTZ_MaxDevicesError = -6L, /* Maximum number of devices exceeded */
197 CAEN_DGTZ_BadBoardType = -7L, /* The operation is not allowed on this type of board */
198 CAEN_DGTZ_BadInterruptLev = -8L, /* The interrupt level is not allowed */
199 CAEN_DGTZ_BadEventNumber = -9L, /* The event number is bad */
200 CAEN_DGTZ_ReadDeviceRegisterFail = -10L, /* Unable to read the registry */
201 CAEN_DGTZ_WriteDeviceRegisterFail = -11L, /* Unable to write into the registry */
202 CAEN_DGTZ_InvalidChannelNumber = -13L, /* The channel number is invalid */
203 CAEN_DGTZ_ChannelBusy = -14L, /* The Channel is busy */
204 CAEN_DGTZ_FPIOModeInvalid = -15L, /* Invalid FPIO Mode */
205 CAEN_DGTZ_WrongAcqMode = -16L, /* Wrong acquisition mode */
206 CAEN_DGTZ_FunctionNotAllowed = -17L, /* This function is not allowed for this module */
207 CAEN_DGTZ_Timeout = -18L, /* Communication Timeout */
208 CAEN_DGTZ_InvalidBuffer = -19L, /* The buffer is invalid */
209 CAEN_DGTZ_EventNotFound = -20L, /* The event is not found */
210 CAEN_DGTZ_InvalidEvent = -21L, /* The vent is invalid */
211 CAEN_DGTZ_OutOfMemory = -22L, /* Out of memory */
212 CAEN_DGTZ_CalibrationError = -23L, /* Unable to calibrate the board */
213 CAEN_DGTZ_DigitizerNotFound = -24L, /* Unable to open the digitizer */
214 CAEN_DGTZ_DigitizerAlreadyOpen = -25L, /* The Digitizer is already open */
215 CAEN_DGTZ_DigitizerNotReady = -26L, /* The Digitizer is not ready to operate */
216 CAEN_DGTZ_InterruptNotConfigured = -27L, /* The Digitizer has not the IRQ configured */
217 CAEN_DGTZ_DigitizerMemoryCorrupted = -28L, /* The digitizer flash memory is corrupted */
218 CAEN_DGTZ_DPPFirmwareNotSupported = -29L, /* The digitizer dpp firmware is not supported in this lib version */
219 
220 CAEN_DGTZ_NotYetImplemented = -99L, /* The function is not yet implemented */
221 
223 
224 #define CAEN_DGTZ_MAX_CHANNEL 8
227 /*###########################################################################*/
228 /*
229 ** ConnectionType
230 */
231 /*###########################################################################*/
232 
239 
240 
241 /* Digitizers Model */
242 typedef enum
243 {
275 
276 typedef enum {
282 
283 typedef enum {
295 
297 {
321 
322 typedef enum
323 {
328 
329 typedef enum
330 {
336 
337 typedef enum {
347 
348 typedef enum
349 {
355 
356 typedef enum
357 {
361 
362 typedef enum
363 {
367 
368 
369 typedef enum
370 {
374 
375 typedef enum
376 {
383 
384 typedef enum
385 {
391 
392 
393 typedef enum
394 {
398 
399 typedef enum
400 {
404 
405 typedef enum
406 {
412 
413 typedef enum
414 {
422 
423 typedef enum
424 {
429 
430 typedef enum
431 {
436 
437 typedef enum {
448 
453 typedef enum
454 {
458 
463 typedef enum
464 {
474 
479 typedef enum
480 {
486 
491 typedef enum
492 {
499 
500 
505 typedef enum
506 {
509 
514 typedef enum
515 {
516  /************************************************************
517  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
518  * The following values are valid for the following DPP-CI *
519  * Firmwares: *
520  * x720 Boards: AMC_REL <= 130.20 *
521  * For newer firmwares, use the values marked with 'R22' in *
522  * the name. *
523  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
524  ************************************************************/
529 
530  /************************************************************
531  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
532  * The following values are valid for the following DPP-CI *
533  * Firmwares: *
534  * x720 Boards: AMC_REL >= 130.22 *
535  * For older firmwares, use the values above. *
536  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
537  ************************************************************/
544 
549 typedef enum
550 {
551  /************************************************************
552  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
553  * The following values are valid for the following DPP-CI *
554  * Firmwares: *
555  * x720 Boards: AMC_REL <= 130.20 *
556  * For newer firmwares, use the values marked with 'R22' in *
557  * the name. *
558  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
559  ************************************************************/
564 
565  /************************************************************
566  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
567  * The following values are valid for the following DPP-CI *
568  * Firmwares: *
569  * x720 Boards: AMC_REL >= 130.22 *
570  * For older firmwares, use the values above. *
571  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
572  ************************************************************/
578 
583 typedef enum
584 {
588 
593 typedef enum
594 {
595  /************************************************************
596  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
597  * The following values are valid for the following DPP-PSD *
598  * Firmwares: *
599  * x720 Boards: AMC_REL <= 131.5 *
600  * x751 Boards: AMC_REL <= 132.5 *
601  * For newer firmwares, use the values marked with 'R6' in *
602  * the name. *
603  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
604  ************************************************************/
605 
606  /* x720 Digital Probes Types */
615 
616  /* x751 Digital Probes Types */
620 
621  /************************************************************
622  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
623  * The following values are valid for the following DPP-PSD *
624  * Firmwares: *
625  * x720 Boards: AMC_REL >= 131.6 *
626  * x751 Boards: AMC_REL >= 132.6 *
627  * For older firmwares, use the values above. *
628  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
629  ************************************************************/
638 
643 typedef enum
644 {
645  /************************************************************
646  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
647  * The following values are valid for the following DPP-PSD *
648  * Firmwares: *
649  * x720 Boards: AMC_REL <= 131.5 *
650  * x751 Boards: AMC_REL <= 132.5 *
651  * For newer firmwares, use the values marked with 'R6' in *
652  * the name. *
653  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
654  ************************************************************/
655 
656  /* x720 Digital Probes Types */
665 
666  /* x751 Digital Probes Types */
670 
671  /************************************************************
672  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
673  * The following values are valid for the following DPP-PSD *
674  * Firmwares: *
675  * x720 Boards: AMC_REL >= 131.6 *
676  * x751 Boards: AMC_REL >= 132.6 *
677  * For older firmwares, use the values above. *
678  * WARNING WARNING WARNING WARNING WARNING WARNING WARNING *
679  ************************************************************/
687 
691 typedef enum
692 {
699 
700 typedef enum {
704 
705 typedef enum {
711 
712 typedef enum {
721 typedef enum {
728 
729 
730 typedef enum {
734 
735 typedef enum {
739 
740 typedef struct {
741  char ModelName[12];
742  uint32_t Model;
743  uint32_t Channels;
744  uint32_t FormFactor;
745  uint32_t FamilyCode;
746  char ROC_FirmwareRel[20];
747  char AMC_FirmwareRel[40];
748  uint32_t SerialNumber;
749  uint32_t PCB_Revision;
750  uint32_t ADC_NBits;
752 
753 typedef struct
754 {
755  uint32_t EventSize;
756  uint32_t BoardId;
757  uint32_t Pattern;
758  uint32_t ChannelMask;
759  uint32_t EventCounter;
760  uint32_t TriggerTimeTag;
762 
763 typedef struct
764 {
765  uint32_t ChSize[MAX_X742_CHANNEL_SIZE]; // the number of samples stored in DataChannel array
766  float *DataChannel[MAX_X742_CHANNEL_SIZE]; // the array of ChSize samples
767  uint32_t TriggerTimeTag;
768  uint16_t StartIndexCell;
770 
771 typedef struct
772 {
773  uint32_t ChSize; // the number of samples stored in DataChannel array
774  float *DataChannel[MAX_X743_CHANNELS_X_GROUP]; // the array of ChSize samples
776  uint16_t TriggerCount;
777  uint16_t TimeCount;
778  uint8_t EventId;
779  uint16_t StartIndexCell;
781 
782 typedef struct
783 {
784  uint32_t ChSize[MAX_UINT16_CHANNEL_SIZE]; // the number of samples stored in DataChannel array
785  uint16_t *DataChannel[MAX_UINT16_CHANNEL_SIZE]; // the array of ChSize samples
787 
788 typedef struct
789 {
790  uint32_t ChSize[MAX_UINT8_CHANNEL_SIZE]; // the number of samples stored in DataChannel array
791  uint8_t *DataChannel[MAX_UINT8_CHANNEL_SIZE]; // the array of ChSize samples
793 
794 typedef struct
795 {
796  uint8_t GrPresent[MAX_X742_GROUP_SIZE]; // If the group has data the value is 1 otherwise is 0
797  CAEN_DGTZ_X742_GROUP_t DataGroup[MAX_X742_GROUP_SIZE]; // the array of ChSize samples
799 
800 typedef struct
801 {
802  uint8_t GrPresent[MAX_V1743_GROUP_SIZE]; // If the group has data the value is 1 otherwise is 0
803  CAEN_DGTZ_X743_GROUP_t DataGroup[MAX_V1743_GROUP_SIZE]; // the array of ChSize samples
805 
809 typedef struct
810 {
811  uint32_t Format;
812  uint64_t TimeTag;
813  uint16_t Energy;
814  int16_t Extras;
815  uint32_t *Waveforms;
818 
822 typedef struct
823 {
824  uint32_t Format;
825  uint32_t TimeTag;
826  int16_t ChargeShort;
827  int16_t ChargeLong;
828  int16_t Baseline;
829  int16_t Pur;
830  uint32_t *Waveforms;
832 
836 typedef struct
837 {
838  uint32_t Format;
839  uint32_t TimeTag;
840  int16_t Charge;
841  int16_t Baseline;
842  uint32_t *Waveforms;
844 
848 typedef struct
849 {
850  uint32_t timeTag;
851  uint32_t baseline;
852  uint32_t *Waveforms;
854 
855 
856 typedef struct
857 {
858  uint32_t size;
859  float *Charge;
861 
865 typedef struct
866 {
867  uint32_t Ns;
868  uint8_t DualTrace;
869  uint8_t VProbe1;
870  uint8_t VProbe2;
871  uint8_t VDProbe;
872  int16_t *Trace1;
873  int16_t *Trace2;
874  uint8_t *DTrace1;
875  uint8_t *DTrace2;
877 
881 typedef struct
882 {
883  uint32_t Ns;
884  uint8_t dualTrace;
885  uint8_t anlgProbe;
886  uint8_t dgtProbe1;
887  uint8_t dgtProbe2;
888  uint16_t *Trace1;
889  uint16_t *Trace2;
890  uint8_t *DTrace1;
891  uint8_t *DTrace2;
892  uint8_t *DTrace3;
893  uint8_t *DTrace4;
895 
896 
900 typedef struct
901 {
902  uint32_t Ns;
903  uint16_t *Trace1;
904  uint8_t *Discarded;
906 
907 #define CAEN_DGTZ_DPP_CI_Waveforms_t CAEN_DGTZ_DPP_PSD_Waveforms_t
909 #define CAEN_DGTZ_AutoAggregation 0
910 
915 typedef enum
916 {
920 #define CAEN_DGTZ_DPP_CI_PUR_DetectOnly CAEN_DGTZ_DPP_PSD_PUR_DetectOnly
921 #define CAEN_DGTZ_DPP_CI_PUR_Enabled CAEN_DGTZ_DPP_PSD_PUR_Enabled
927 typedef enum
928 {
932 
937 typedef enum
938 {
942 
943 
944 typedef enum
945 {
951 
956 typedef struct
957 {
958  int M [MAX_V1724DPP_CHANNEL_SIZE]; // Signal Decay Time Constant
959  int m [MAX_V1724DPP_CHANNEL_SIZE]; // Trapezoid Flat Top
960  int k [MAX_V1724DPP_CHANNEL_SIZE]; // Trapezoid Rise Time
962  int a [MAX_V1724DPP_CHANNEL_SIZE]; // Trigger Filter smoothing factor
963  int b [MAX_V1724DPP_CHANNEL_SIZE]; // Input Signal Rise time
964  int thr [MAX_V1724DPP_CHANNEL_SIZE]; // Trigger Threshold
965  int nsbl [MAX_V1724DPP_CHANNEL_SIZE]; // Number of Samples for Baseline Mean
966  int nspk [MAX_V1724DPP_CHANNEL_SIZE]; // Number of Samples for Peak Mean Calculation
967  int pkho [MAX_V1724DPP_CHANNEL_SIZE]; // Peak Hold Off
968  int blho [MAX_V1724DPP_CHANNEL_SIZE]; // Base Line Hold Off
969  int otrej [MAX_V1724DPP_CHANNEL_SIZE]; //
970  int trgho [MAX_V1724DPP_CHANNEL_SIZE]; // Trigger Hold Off
971  int twwdt [MAX_V1724DPP_CHANNEL_SIZE]; //
972  int trgwin [MAX_V1724DPP_CHANNEL_SIZE]; //
973  int dgain [MAX_V1724DPP_CHANNEL_SIZE]; // Digital Probe Gain
974  float enf [MAX_V1724DPP_CHANNEL_SIZE]; // Energy Nomralization Factor
975  int decimation[MAX_V1724DPP_CHANNEL_SIZE]; // Decimation of Input Signal
977 
982 typedef struct {
983  int blthr;
984  int bltmo;
985  int trgho;
994  CAEN_DGTZ_DPP_TriggerConfig_t trgc // Ignored for x751
996  CAEN_DGTZ_DPP_PUR_t purh; // Ignored for x751
997  int purgap; // Ignored for x751
999 
1000 
1005 typedef struct {
1006  int blthr;
1007  int bltmo;
1008  int trgho;
1019 
1020 typedef struct {
1021  int NSampBck [MAX_ZLE_CHANNEL_SIZE];
1022  int NSampAhe [MAX_ZLE_CHANNEL_SIZE];
1023  int ZleUppThr [MAX_ZLE_CHANNEL_SIZE];
1024  int ZleUndThr [MAX_ZLE_CHANNEL_SIZE];
1025  int selNumSampBsl [MAX_ZLE_CHANNEL_SIZE];
1026  int bslThrshld [MAX_ZLE_CHANNEL_SIZE];
1027  int bslTimeOut [MAX_ZLE_CHANNEL_SIZE];
1028  int preTrgg;
1030 typedef struct {
1035 
1036 
1037 typedef enum {
1043 #endif
1044