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| #define | VERSION(ver, rel, seq) (((ver)<<16) | ((rel)<<8) | (seq)) |
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| #define | MIN_DMA_SIZE (80) |
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| #define | MAX_MINOR (256) |
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| #define | PFX "a3818: " |
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| #define | MAX_V2718 (8) |
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| #define | A3818_MAX_PKT_SZ (0x20000) |
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| #define | A3818_RXFIFO_SZ (0x2000) |
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| #define | A3818_REGION_SIZE (0x100) |
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| #define | PCI_VENDOR_XILINX_ID (0x10ee) |
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| #define | PCI_DEVICE_ID_VIRTEX (0x0007) |
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| #define | PCI_SUBSYSTEM_VENDOR_ID_XILINX (0x10ee) |
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| #define | PCI_SUBSYSTEM_ID_VIRTEX (0x0007) |
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| #define | A3818_MAGIC '8' |
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| #define | IOCTL_RESET _IO(A3818_MAGIC, 0) |
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| #define | IOCTL_COMM _IOWR(A3818_MAGIC, 1, a3818_comm_t) |
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| #define | IOCTL_REG_WR _IOW(A3818_MAGIC, 2, a3818_reg_t) |
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| #define | IOCTL_REG_RD _IOWR(A3818_MAGIC, 3, a3818_reg_t) |
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| #define | IOCTL_IRQ_WAIT _IOW(A3818_MAGIC, 4, a3818_intr_t) |
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| #define | IOCTL_SEND _IOWR(A3818_MAGIC, 5, a3818_comm_t) |
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| #define | IOCTL_RECV _IOWR(A3818_MAGIC, 6, int) |
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| #define | IOCTL_REV _IOWR(A3818_MAGIC, 7, a3818_rev_t) |
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| #define | IOCTL_COMM_REG_WR _IOW(A3818_MAGIC, 8, a3818_reg_t) |
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| #define | IOCTL_COMM_REG_RD _IOWR(A3818_MAGIC, 9, a3818_reg_t) |
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| #define | A3818_IOCTL_START_DMA_TO_PC _IOWR(A3818_MAGIC, 10, a3818_comm_t) |
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| #define | PCI_IOCTL_REG_RD _IOWR(A3818_MAGIC, 11, a3818_reg_t) |
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| #define | A3818_IOCTL_PCIE_BRIDGE_RESET _IO(A3818_MAGIC, 12) |
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| #define | IOCTL_MATI _IO(A3818_MAGIC, 13) |
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| #define | START_WRITE_DMA (0x01) |
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| #define | MAX_OPT_LINK (0x05) |
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| #define | A3818_COMMON_REG (0x05) |
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| #define | AT45DB321D_PAGE_SIZE 264 |
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| #define | MAX_TLP32_DATA_PAYLOAD 32 |
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| #define | A3818_OK 0 |
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| #define | A3818_ERR_NOT_READY 1 |
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| #define | A3818_TXFIFO (0x00) |
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| #define | A3818_RXFIFO (0x04) |
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| #define | IOCTL (0x08) |
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| #define | A3818_LNKRST (1) |
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| #define | A3818_RDYINTDIS (1 << 1) |
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| #define | A3818_SERVICE (1 << 2) |
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| #define | A3818_VINTDIS (1 << 3) |
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| #define | A3818_RES_LOCINT (1 << 4) |
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| #define | A3818_LINK_SR (0x0C) |
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| #define | A3818_RXFIFO_EMPTY (1) |
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| #define | A3818_RXFIFO_ALMFULL (1 << 1) |
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| #define | A3818_TXFIFO_FULL (1 << 2) |
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| #define | A3818_VMEINT (1 << 3) |
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| #define | A3818_LINKON (1 << 5) |
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| #define | A3818_LINKRST_STAT (1 << 6) |
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| #define | A3818_SERV (1 << 7) |
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| #define | A3818_LINK_FAIL (1 << 8) |
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| #define | A3818_LINT (1 << 9) |
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| #define | A3818_LINK_TX_RES (1 << 16) |
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| #define | A3818_LINK_RX_RES (1 << 17) |
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| #define | A3818_LINK_TRS (0x18) |
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| #define | A3818_DEBUG (0x20) |
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| #define | A3818_IRQSTAT_0 (0x24) |
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| #define | A3818_IRQSTAT_1 (0x28) |
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| #define | A3818_IRQMASK_0_S (0x30) |
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| #define | A3818_IRQMASK_0_C (0x34) |
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| #define | A3818_IRQMASK_1_S (0x38) |
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| #define | A3818_IRQMASK_1_C (0x3C) |
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| #define | A3818_IOCTL_S (0xA0) |
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| #define | A3818_IOCTL_C (0xA4) |
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| #define | A3818_DMACSR (0x100) |
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| #define | A3818_DMAREADSTART (1 << 0) |
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| #define | A3818_DMAREADDONE (1 << 8) |
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| #define | A3818_RES_DMAINT (1 << 31) |
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| #define | A3818_RDMATLPA (0x104) |
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| #define | A3818_RDMALADR (0x108) |
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| #define | A3818_RDMASIZE (0x10C) |
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| #define | A3818_RDMAMODE (0x110) |
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| #define | A3818_DMAMODE_INTDIS (1 << 6) |
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| #define | A3818_WDMAPERF (0x114) |
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| #define | A3818_DMACSR_S (0x118) |
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| #define | A3818_DLWSTAT (0x00) |
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| #define | A3818_DLTRSSTAT (0x04) |
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| #define | A3818_DMISCCS (0x08) |
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| #define | A3818_DMISCCS_CPL_STREAM (1 << 0) |
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| #define | A3818_DMISCCS_RD_METERING (1 << 1) |
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| #define | A3818_DMISCCS_REC_NON_POSTED_OK (1 << 2) |
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| #define | A3818_DMISCCS_SPI_BPI_FLASH_SEL (1 << 4) |
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| #define | A3818_DMISCCS_SPI_FLASH_RDY (1 << 5) |
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| #define | A3818_DMISCCS_ADC_CLK_SEL (1 << 6) |
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| #define | A3818_DMISCCS_V_PB_EN (1 << 7) |
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| #define | A3818_DMISCCS_RDDMA_DONE0 (1 << 16) |
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| #define | A3818_DMISCCS_RDDMA_DONE1 (1 << 17) |
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| #define | A3818_DMISCCS_RDDMA_DONE2 (1 << 18) |
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| #define | A3818_DMISCCS_RDDMA_DONE3 (1 << 19) |
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| #define | A3818_DMISCCS_RDDMA_DONE4 (1 << 20) |
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| #define | A3818_DMISCCS_LOC_INT0 (1 << 24) |
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| #define | A3818_DMISCCS_LOC_INT1 (1 << 25) |
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| #define | A3818_DMISCCS_LOC_INT2 (1 << 26) |
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| #define | A3818_DMISCCS_LOC_INT3 (1 << 27) |
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| #define | A3818_DMISCCS_LOC_INT4 (1 << 28) |
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| #define | A3818_GTPRES (0x0C) |
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| #define | A3818_SPI_FLASH (0x10) |
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| #define | A3818_SPI_FLEN (0x14) |
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| #define | A3818_SPI_RELOAD (0x18) |
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| #define | A3818_BPI_FLASH_AD (0x20) |
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| #define | A3818_BPI_FLASH_DT (0x24) |
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| #define | A3818_BPI_FLASH_CMD (0x28) |
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| #define | A3818_PHY_I2C_COMM (0x30) |
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| #define | A3818_PHY_I2C_DAT (0x34) |
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| #define | A3818_ADC_I2C_COMM (0x38) |
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| #define | A3818_ADC_I2C_DAT (0x3C) |
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| #define | A3818_FWREV (0x40) |
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| #define | A3818_BOARD_ID (0x44) |
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| #define | A3818_BOARD_VERS_ID (0x48) |
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| #define | A3818_BOARD_SERNUM (0x4C) |
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| #define | A3818_TEMP (0x50) |
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| #define | A3818_SSRAM_AD (0x60) |
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| #define | A3818_SSRAM_DT_L (0x64) |
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| #define | A3818_SSRAM_DT_M (0x68) |
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| #define | A3818_SSRAM_DT_H (0x6C) |
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| #define | A3818_SSRAM_CMD (0x70) |
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| #define | A3818BOARD (0x0eea) |
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| #define | ONE_LINK (0x0a) |
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| #define | TWO_LINK (0x0b) |
| |
| #define | FOUR_LINK (0x0c) |
| |
| #define | A3818DIGIT (0x0d) |
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| #define | A3818RAW (0xffffff) |
| |
| #define | PCIE_DMA_CONF_REG (0x68) |
| |
| #define | PCIE_MSI_CAPAB_REG (0x48) |
| |
| #define | A3818_DRIVER_VERSION_LEN 20 |
| |
