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a3818.h
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1 /*
2  ----------------------------------------------------------------------
3 
4  --- CAEN SpA - Computing Systems Division ---
5 
6  a3818.h
7 
8  Header file for the CAEN A3818 HS CONET board driver.
9 
10  November 2008 : Modified for A3818
11  June 2004 : Created (a2818).
12 
13  ----------------------------------------------------------------------
14 */
15 #ifndef _a3818_H
16 #define _a3818_H
17 
18 #ifndef VERSION
19  #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
20 #endif
21 
22 
23 
24 #ifdef WIN32
25 #include <windows.h>
26  #ifndef int8_t
27  #define int8_t INT8
28  #endif
29  #ifndef int16_t
30  #define int16_t INT16
31  #endif
32  #ifndef int32_t
33  #define int32_t INT32
34  #endif
35  #ifndef int64_t
36  #define int64_t INT64
37  #endif
38  #ifndef uint8_t
39  #define uint8_t UINT8
40  #endif
41  #ifndef uint16_t
42  #define uint16_t UINT16
43  #endif
44  #ifndef uint32_t
45  #define uint32_t UINT32
46  #endif
47  #ifndef uint64_t
48  #define uint64_t UINT64
49  #endif
50 #endif
51 
52 //#define DEBUG 1
53 /*
54  Defines for the a3818
55 */
56 #define MIN_DMA_SIZE (80)
57 #define MAX_MINOR (256)
58 #define PFX "a3818: "
59 
60 #define MAX_V2718 (8)
61 
62 #define A3818_MAX_PKT_SZ (0x20000)
63 
64 #define A3818_RXFIFO_SZ (0x2000)
65 #define A3818_REGION_SIZE (0x100)
66 
67 #define PCI_VENDOR_XILINX_ID (0x10ee) // XILINX
68 #define PCI_DEVICE_ID_VIRTEX (0x0007) // VIRTEX5
69 #define PCI_SUBSYSTEM_VENDOR_ID_XILINX (0x10ee)
70 #define PCI_SUBSYSTEM_ID_VIRTEX (0x0007)
71 
72 #define A3818_MAGIC '8'
73 
74 #define IOCTL_RESET _IO(A3818_MAGIC, 0)
75 #define IOCTL_COMM _IOWR(A3818_MAGIC, 1, a3818_comm_t)
76 #define IOCTL_REG_WR _IOW(A3818_MAGIC, 2, a3818_reg_t)
77 #define IOCTL_REG_RD _IOWR(A3818_MAGIC, 3, a3818_reg_t)
78 #define IOCTL_IRQ_WAIT _IOW(A3818_MAGIC, 4, a3818_intr_t)
79 #define IOCTL_SEND _IOWR(A3818_MAGIC, 5, a3818_comm_t)
80 #define IOCTL_RECV _IOWR(A3818_MAGIC, 6, int)
81 #define IOCTL_REV _IOWR(A3818_MAGIC, 7, a3818_rev_t)
82 #define IOCTL_COMM_REG_WR _IOW(A3818_MAGIC, 8, a3818_reg_t)
83 #define IOCTL_COMM_REG_RD _IOWR(A3818_MAGIC, 9, a3818_reg_t)
84 
85 #define A3818_IOCTL_START_DMA_TO_PC _IOWR(A3818_MAGIC, 10, a3818_comm_t) // AM per debug su DMA dalla A3818 al PC
86 #define PCI_IOCTL_REG_RD _IOWR(A3818_MAGIC, 11, a3818_reg_t) // AM per conoscere i registro del PCI
87 #define A3818_IOCTL_PCIE_BRIDGE_RESET _IO(A3818_MAGIC, 12)
88 #define IOCTL_MATI _IO(A3818_MAGIC, 13)
89 
90 #define START_WRITE_DMA (0x01) // AM Write to PC in DMA da togliere!!!
91 
92 #define MAX_OPT_LINK (0x05)
93 #define A3818_COMMON_REG (0x05)
94 
95 #define AT45DB321D_PAGE_SIZE 264 // AUG!
96 
97 #define MAX_TLP32_DATA_PAYLOAD 32
98 
99 /************************************************/
100 /* A3818 ERROR MESSAGES */
101 #define A3818_OK 0
102 #define A3818_ERR_NOT_READY 1
103 
104 /************************************************
105  A3818 Registers offsets & bits
106 *************************************************/
107 /************************************************/
108 /* LINK REGISTERS */
109 #define A3818_TXFIFO (0x00)
110 #define A3818_RXFIFO (0x04)
111 #define IOCTL (0x08)
112 # define A3818_LNKRST (1) // Link Reset
113 # define A3818_RDYINTDIS (1 << 1)// Disable interrupt for data ready
114 # define A3818_SERVICE (1 << 2)// SERV mode del CONET
115 # define A3818_VINTDIS (1 << 3)// Disable interrupt from VME
116 # define A3818_RES_LOCINT (1 << 4)// Reset Local Interrupt
117 
118 #define A3818_LINK_SR (0x0C) // link status register
119 # define A3818_RXFIFO_EMPTY (1)
120 # define A3818_RXFIFO_ALMFULL (1 << 1)
121 # define A3818_TXFIFO_FULL (1 << 2)
122 # define A3818_VMEINT (1 << 3)
123 
124 # define A3818_LINKON (1 << 5)
125 # define A3818_LINKRST_STAT (1 << 6)
126 # define A3818_SERV (1 << 7)
127 # define A3818_LINK_FAIL (1 << 8)
128 # define A3818_LINT (1 << 9)
129 
130 # define A3818_LINK_TX_RES (1 << 16)
131 # define A3818_LINK_RX_RES (1 << 17)
132 
133 #define A3818_LINK_TRS (0x18) // link transfer status register
134 
135 #define A3818_DEBUG (0x20)
136 
137 #define A3818_IRQSTAT_0 (0x24) // IRQ Stat dagli slave 0 to 3
138 #define A3818_IRQSTAT_1 (0x28) // IRQ Stat dagli slave 4 to 7
139 #define A3818_IRQMASK_0_S (0x30) // IRQ Mask slave 0 to 3 - Set
140 #define A3818_IRQMASK_0_C (0x34) // IRQ Mask slave 0 to 3 - Clear
141 #define A3818_IRQMASK_1_S (0x38) // IRQ Mask slave 4 to 7 - Set
142 #define A3818_IRQMASK_1_C (0x3C) // IRQ Mask slave 4 to 7 - Clear
143 
144 #define A3818_IOCTL_S (0xA0) // - IOCTL register set
145 #define A3818_IOCTL_C (0xA4) // - IOCTL register clear
146 
147 /* DMA LINK REGISTERS*/
148 #define A3818_DMACSR (0x100) // DMA Control Status Register
149 # define A3818_DMAREADSTART (1 << 0) // DMA Memory Read Start
150 # define A3818_DMAREADDONE (1 << 8) // DMA Memory Read Done
151 # define A3818_RES_DMAINT (1 << 31) // DMA Initiator Reset
152 
153 #define A3818_RDMATLPA (0x104) // Read DMA Memory Address
154 #define A3818_RDMALADR (0x108) // Read DMA Local Address
155 #define A3818_RDMASIZE (0x10C) // Read DMA Size
156 
157 #define A3818_RDMAMODE (0x110) // Read DMA Mode
158 # define A3818_DMAMODE_INTDIS (1 << 6) // Read Interrupt Disable
159 
160 #define A3818_WDMAPERF (0x114) // DMA Performances Write to PC
161 
162 #define A3818_DMACSR_S (0x118) // DMA Control Status Register - register set
163 
164 /************************************************/
165 /* A3818 COMMON REGISTER */
166 #define A3818_DLWSTAT (0x00) // Device Link Width Status
167 #define A3818_DLTRSSTAT (0x04) // Device Link Transaction Size Status
168 #define A3818_DMISCCS (0x08) // Device Miscellaneous Control Status
169 
170 # define A3818_DMISCCS_CPL_STREAM (1 << 0) // Completion Streaming Enable (default 1)
171 # define A3818_DMISCCS_RD_METERING (1 << 1) // Read Metering Enable (default 0)
172 # define A3818_DMISCCS_REC_NON_POSTED_OK (1 << 2) // Receive Non-Posted OK (default 0)
173 
174 # define A3818_DMISCCS_SPI_BPI_FLASH_SEL (1 << 4) // BPI/SPI FLASH access select (default 0 = SPI FLASH)
175 # define A3818_DMISCCS_SPI_FLASH_RDY (1 << 5) // ATMEL SPI Flash Memory Ready (RO)
176 # define A3818_DMISCCS_ADC_CLK_SEL (1 << 6) // ADC CLK Select (default 1 = SI571 clock)
177 # define A3818_DMISCCS_V_PB_EN (1 << 7) // PB Power enable (default 1 = PB Power ON)
178 
179 # define A3818_DMISCCS_RDDMA_DONE0 (1 << 16)// Link 0 DMA READ Done (RO)
180 # define A3818_DMISCCS_RDDMA_DONE1 (1 << 17)// Link 1 DMA READ Done (RO)
181 # define A3818_DMISCCS_RDDMA_DONE2 (1 << 18)// Link 2 DMA READ Done (RO)
182 # define A3818_DMISCCS_RDDMA_DONE3 (1 << 19)// Link 3 DMA READ Done (RO)
183 # define A3818_DMISCCS_RDDMA_DONE4 (1 << 20)// Link 4 Memory Write Done (RO)
184 
185 # define A3818_DMISCCS_LOC_INT0 (1 << 24)// Link 0 Local Interrupt (RO)
186 # define A3818_DMISCCS_LOC_INT1 (1 << 25)// Link 1 Local Interrupt (RO)
187 # define A3818_DMISCCS_LOC_INT2 (1 << 26)// Link 2 Local Interrupt (RO)
188 # define A3818_DMISCCS_LOC_INT3 (1 << 27)// Link 3 Local Interrupt (RO)
189 # define A3818_DMISCCS_LOC_INT4 (1 << 28)// Link 4 Local Interrupt (RO)
190 
191 #define A3818_GTPRES (0x0C) // W - GTP reset
192 
193 #define A3818_SPI_FLASH (0x10) // R/W - ATMEL SPI Flash Memory access
194 #define A3818_SPI_FLEN (0x14) // R/W - ATMEL SPI Flash Memory enable
195 #define A3818_SPI_RELOAD (0x18) // W - Re-read the SPI flash content
196 
197 #define A3818_BPI_FLASH_AD (0x20) // R/W - BPI_FLASH TEST
198 #define A3818_BPI_FLASH_DT (0x24) // R/W
199 #define A3818_BPI_FLASH_CMD (0x28) // R/W
200 
201 #define A3818_PHY_I2C_COMM (0x30) // W
202 #define A3818_PHY_I2C_DAT (0x34) // R
203 
204 #define A3818_ADC_I2C_COMM (0x38) // W
205 #define A3818_ADC_I2C_DAT (0x3C) // R
206 
207 #define A3818_FWREV (0x40) // R - Firmware Revision
208 #define A3818_BOARD_ID (0x44) // R - Board ID
209 #define A3818_BOARD_VERS_ID (0x48) // R - Board Version ID
210 #define A3818_BOARD_SERNUM (0x4C) // R - Board Serial Number
211 #define A3818_TEMP (0x50) // R - rilettura del sensore di temp. TMP422
212 
213 #define A3818_SSRAM_AD (0x60) // R/W - SSRAM TEST
214 #define A3818_SSRAM_DT_L (0x64) // R/W
215 #define A3818_SSRAM_DT_M (0x68) // R/W
216 #define A3818_SSRAM_DT_H (0x6C) // R/W
217 #define A3818_SSRAM_CMD (0x70) // R/W - SSRAM TEST
218 /************************************************/
219 
220 
221 #define A3818BOARD (0x0eea)
222 # define ONE_LINK (0x0a)
223 # define TWO_LINK (0x0b)
224 # define FOUR_LINK (0x0c)
225 
226 #define A3818DIGIT (0x0d)
227 #define A3818RAW (0xffffff)
228 
229 // Registri PCIE
230 #define PCIE_DMA_CONF_REG (0x68)
231 #define PCIE_MSI_CAPAB_REG (0x48)
232 
233 /*
234 #ifdef DEBUG
235 #define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
236 #else
237 #define DPRINTK(format,args...)
238 #endif
239 */
240 
241 #ifdef __KERNEL__
242 
243 /*
244  ----------------------------------------------------------------------
245 
246  Types
247 
248  ----------------------------------------------------------------------
249 */
250 struct a3818_state {
251  /* Common globals */
252  unsigned char *baseaddr[MAX_OPT_LINK + 1]; // reindirizzamento dei 5 base address del pci
253  unsigned long phys[MAX_OPT_LINK + 1]; // indirizzo fisico dei 5 base address del pci
254 
255  struct pci_dev *pcidev;
256  int irq;
257  int minor;
258  int timeout;
259  int NumOfLink;
260  int TypeOfBoard;
261 
262  int SlaveOnLink[MAX_OPT_LINK]; // per conoscere lo slave associato al link utilizzato
263 
264  unsigned char *buff_dma_in[MAX_OPT_LINK]; // buffer per i dma. CPU address.
265  dma_addr_t phy_dma_addr_in[MAX_OPT_LINK]; // PCI address of buff_dma_in.
266  int ndata_dma_in[MAX_OPT_LINK];
267 
268  uint32_t tr_stat[MAX_OPT_LINK];
269 
270  unsigned int reads;
271  unsigned int writes;
272  unsigned int ioctls;
273 
274  unsigned int DMAInProgress[MAX_OPT_LINK];
275 
276  spinlock_t Alock;
277  struct mutex ioctl_lock;
278 
279  /* Per slave globals */
280  uint32_t *buff_dma_out[MAX_OPT_LINK][MAX_V2718];
281  dma_addr_t phy_dma_addr_out[MAX_OPT_LINK][MAX_V2718];
282  wait_queue_head_t read_wait[MAX_OPT_LINK][MAX_V2718];
283  wait_queue_head_t intr_wait[MAX_OPT_LINK][MAX_V2718];
284 
285  wait_queue_head_t read_wait_debug[MAX_OPT_LINK]; // AM per debug
286 
287  unsigned char *app_dma_in[MAX_OPT_LINK][MAX_V2718];
288  int pos_app_dma_in[MAX_OPT_LINK][MAX_V2718];
289  int ndata_app_dma_in[MAX_OPT_LINK][MAX_V2718];
290  int rx_ready[MAX_OPT_LINK][MAX_V2718];
291  int rx_status[MAX_OPT_LINK][MAX_V2718];
292  unsigned int intr[MAX_OPT_LINK][MAX_V2718];
293 
294  int rx_ready_debug[MAX_OPT_LINK]; // AM per debug
295 
296 
297  /* we keep a3818 cards in a linked list */
298  struct a3818_state *next;
299 };
300 #endif
301 /*
302  Struct for communication argument in ioctl calls
303 */
304 typedef struct a3818_comm {
305  const char *out_buf;
306  int out_count;
307  char *in_buf;
308  int in_count;
309  int *status;
310 } a3818_comm_t;
311 
312 /*
313  Struct for register argument in ioctl calls
314 */
315 typedef struct a3818_reg {
316 /* Rev. 1.6 */
317  uint32_t address;
318  uint32_t value;
319 } a3818_reg_t;
320 
321 /*
322  Struct for interrupt argument in ioctl calls
323 */
324 typedef struct a3818_intr {
325  unsigned int Mask;
326  unsigned int Timeout;
327 } a3818_intr_t;
328 
329 // Rev 1.5
330 /*
331  Struct for revision argument in ioctl calls
332 */
333 #define A3818_DRIVER_VERSION_LEN 20
334 typedef struct a3818_rev {
335  char rev_buf[A3818_DRIVER_VERSION_LEN];
336 } a3818_rev_t;
337 
338 #endif
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